The present invention relates to a multi-processor system, and more particularly to a multi-processor system having a multi-port cache memory which is shared with a plurality of processors.
A multi-processor system using a plurality of microprocessors is now being developed extensively. For example, there is disclosed in JP-A-56-127261 a system having a plurality of processors connected via busses, each processor having its own cache memory in order to attain high performance and reduce bus traffic. Prior to accessing main memory in this system, each processor first accesses its associated cache memory, and only when a miss occurs, the main memory is accessed via a bus.
The problem associated with such a system concerns the coherence control of cache memories. The coherence control is effected so as to make the contents of cache memories of all processors always coincident with each other. In the system of the above-referenced JP-A-56-127261, a write-through type cache memory system is used wherein, when data is written in a cache memory and the main memory, the write address thereof is supplied to the other cache memories so that the contents of the other cache memories at the same address are made invalid.
Use of such write-through type cache memories results in a high frequency of write operations into the main memory. In order to further reduce the write operation frequency, algorithms using write-back type cache memories, more improved write-once type cache memories, or the like have been developed. The details of these algorithms are discussed in James R. Goodman "USING CACHE MEMORY TO REDUCE PROCESSOR--MEMORY TRAFFIC", The 10th Annual International Symposium on COMPUTER ARCHITECTURE, Vol. 11, No. 3, Jun., 13-17, 1983.
Cache memories of the above-described types are suitable for those systems executing parallel processings of coarse grain units, such as task or process units. However, parallel processings of fine grain units such as subroutines or modules are associated with a problem that data to be shared with processors become large. A larger amount of shared data results in frequent invalidations of data in cache memories upon a data write operation into the main memory, and in a low hit rate at each cache memory.
The above system configurations have been realized aiming at reducing signal lines for linkage among processors each provided in one LSI chip. However, these configurations will not become optimum if a plurality of processors are fabricated in one LSI chip by employing an ultra very LSI technology.